Level shifter

ABSTRACT

A level shifter having a data input node, a first inverter having its input connected to the data input node, a second inverter connected to an output of the first inverter, a data output node, a latch having its output connected to the data output node, a first NFET connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter, and a second NFET connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter. The level shifter provides for a conversion of a data signal from a power supply domain of 1.8 volts to one of 3.3 volts.

TECHNICAL FIELD

[0001] The present invention relates in general to data processingsystems, and in particular, to the transfer of data signals withinintegrated circuitry.

BACKGROUND INFORMATION

[0002] Level shifting receivers translate signals between two voltagesupply domains. For example, receivers may translate signals originatingfrom an integrated circuit operating under a lower supply voltage (e.g.,1.8 volts (V)) to an integrated circuit operating with a higher supplyvoltage (e.g., 2.5 V). Prior art circuits have also been designed thatpermit the isolation of the receiver from the removal of the driversupply voltage.

[0003] Referring to FIG. 3, there is illustrated prior art level shifter100, wherein the low-voltage supply is designated as Vdd and the highvoltage supply is designated as Vdd_H. The data in input signal isbuffered by inverters operating under the lower supply voltage Vdd. Thefirst inverter is comprised of NFET (N-channel field effect transistor)301 and PFET(P-channel FET) 302, while the second inverter is comprisedof PFET 303 and NFET 304. The complementary outputs of these twoinverters are driven to pull-down NFETs 305 and 308 with cross-coupledPFETs 306 and 307. This prior art circuit has the disadvantage that itdoes not preserve valid signal levels in the event that the voltage Vddis disabled, i.e., either forced to the same potential as the ground orallowed to degrade over time to the ground potential (for example,portable electronic devices employ nonpersisent power supply domainswhere the voltage supply is removed from the circuitry to preservebattery power). In particular, as the supply degrades toward ground, thenodes at the drain of the cross-coupled PFETs will both rise up towithin a threshold voltage of the high voltage supply, Vdd_H.

[0004] In addition, as the voltage Vdd is degrading toward ground, onecannot be certain that the inverters powered by Vdd will maintain theirrelative order: whichever signal amongst the output of the firstinverter, formed by devices 301 and 302, and the output of the secondinverter, formed by devices 303 and 304, which was initially higher involtage may, as the supply degrades, become lower in voltage. Thischange in the relative maximum voltage signal increases powerconsumption and may cause the output DATA OUT to change state.

[0005] When the level shifter is used in an environment where the lowvoltage supply can be removed, for instance to save power, the levelshifter may be augmented with isolation NFETs, such as NFETs 410 and 412shown in the level shifter 400 of FIG. 4. Such isolation NFETs helpprevent transient events during the removal of the Vdd supply fromaffecting the state of the level shifter. Devices 401-404 operatesimilarly to devices 301-304; device 409 operates similarly to device305; devices 406-407 operate similarly to devices 306-307; and device411 operates similarly to device 308. Prior to the removal of Vdd, theHOLD signal is driven low to isolate the shifter 400. To hold the stateof the various signals within the level shifter 400, the cross-coupledNFETs 405 and 408 are added. Thus when Vdd is removed, the state of thelevel shifter 400 when the HOLD signal is removed is maintained.However, the cascaded NFETs 409/410 and 411/412 limit the performance ofthe level shifter, primarily limiting the voltage gain range of theoutput of the shifter. There are two major problems with this prior artcircuit due to the cascaded transistors: the cascaded transistors limitthe difference between the supplies Vdd_H and Vdd, and because thetransistors are cascaded, they must be large which increases circuitarea and power consumption.

[0006] Thus, there is a need in the art for a level shifter thatovercomes the aforementioned deficiencies, thus providing a gain in theactive voltage range of the Vdd supply.

SUMMARY OF THE INVENTION

[0007] The present invention addresses the foregoing needs by allowing asignificantly greater voltage difference between the low and high levelpower supplies in the implementation of level shifters, and supports theremoval of the driver power supply from the low level circuitry whilemaintaining the integrity of the data signal at the high level circuitryoutput side. This is accomplished in part by eliminating the cascadeddevices in the level shifter.

[0008] One embodiment of the present invention is a level shiftercomprising a data input node, a first inverter having its inputconnected to the data input node, a second inverter connected to anoutput of the first inverter, a data output node, a latch having itsoutput connected to the data output node, a first NFET connected betweenan input of the latch and a ground potential, and having its gateelectrode connected to an output of the second inverter, and a secondNFET connected between the data output node and the ground potential,and having its gate electrode connected to the output of the firstinverter.

[0009] Another embodiment of the present invention is as a dataprocessing system comprising a microprocessor and accompanying circuitryoutputting data signals with a voltage swing magnitude of 1.8 volts,level shifter circuitry for converting the voltage swing magnitude ofthe data signals from 1.8 volts to 3.3 volts, and input/output (I/O)circuitry for receiving the data signals with the voltage swingmagnitude of 3.3 volts.

[0010] Another embodiment of the present invention is as a level shiftercomprising first circuitry for receiving a data signal having a voltageswing from ground to 1.8 volts, and second circuitry for converting thedata signal to have a voltage swing from ground to 3.3 volts.

[0011] Another embodiment of the present invention is as a level shiftercomprising a data input node, a first NOR gate coupled to the data inputnode, a second NOR gate coupled to an output of the first NOR gate, astorage cell coupled to an output of the second NOR gate, and a dataoutput node coupled to an output of the storage cell.

[0012] The foregoing has outlined rather broadly the features andtechnical advantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter which form the subject of the claims of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of the present invention, andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawings, inwhich:

[0014]FIG. 1 illustrates a level shifter in accordance with anembodiment of the present invention;

[0015]FIG. 2 illustrates data processing circuitry implementing thelevel shifter of FIG. 1;

[0016]FIG. 3 illustrates a prior art level shifter; and

[0017]FIG. 4 illustrates another prior art level shifter.

DETAILED DESCRIPTION

[0018] In the following description, numerous specific details are setforth to provide a thorough understanding of the present invention.However, it will be obvious to those skilled in the art that the presentinvention may be practiced without such specific details. In otherinstances, well-known circuits have been shown in block diagram form inorder not to obscure the present invention in unnecessary detail. Forthe most part, details concerning timing considerations and the likehave been omitted in as much as such details are not necessary to obtaina complete understanding of the present invention and are within theskills of persons of ordinary skill in the relevant art.

[0019] Refer now to the drawings wherein depicted elements are notnecessarily shown to scale and wherein like or similar elements aredesignated by the same reference numeral through the several views.

[0020] The level shifter of the present invention is applicable tocircuits in which the internal circuitry is operated at a voltage whichis lower than the voltage required for the I/O drivers and receivers,and also where the voltage to the internal circuitry can be disabled tosave power, while the I/O drivers and receivers remain powered andmaintain the voltages on the off-chip signals.

[0021] Referring to FIG. 2, a level shifter 100 operates between twodifferent power supply domains. This environment is typical of low-powerelectronic devices, such as battery-powered devices where conservingenergy is particularly important and where the internal logic voltagestend to be low. An exemplary application is shown in FIG. 2, where amicroprocessor is used in a battery-powered device, where the internallogic is powered by a supply voltage which can be varied from 1.8V to1V, and is not persistent, and where the I/O drivers and receivers whichgenerate and receive the off-chip signals are powered by a 3.3V supplyvoltage. Note that the present invention is not limited to the use inintegrated circuitry of such exact power supply voltages, but isapplicable where any level shifter is needed. In such devices, it isimportant that during the removal of the internal logic voltage supply,that the circuit which receives signals from the internal logic domainand translates these signals to the I/O supply domain not generatetransient signals or glitches, generate indeterminate output levels, orburn excessive power, which are all possible with the prior art circuits300 and 400 shown in FIGS. 3 and 4. During the collapse of the internallogic supply voltage when the supply is disabled, the voltage on thegiven signal may temporarily rise in voltage prior to falling. Thistemporary rise in voltage level may cause the prior art circuits 300 and400 to glitch, go indeterminate, or burn power. The present invention,as shown in FIGS. 1 and 2, allows the receiver to continue to generatevalid I/O voltage domain outputs when the internal logic domain signalsbecome invalid.

[0022] In FIG. 2, a battery 210 supplies power to a supply suspendcontrol logic 204 embodied within a persistent voltage domain 201. Inthis context, a persistent voltage domain is the collection of allcircuitry powered by a voltage which is active at any time in which thedevice is on; the supply is never switched off, driven to ground, orallowed to degrade below its normal operating range whenever the deviceis active. Select and shutdown signals are received from the supplysuspend control logic 204 by the external DC/DC supplies 205, whichsupply various voltages to circuits 202 and 203. The Shutdown signalfrom the supply suspend control logic 204 signals to the external powersupply 205 (e.g., DC-to-DC converter) that the power to the logic shouldbe disabled either by forcing the voltage to ground or allowing thevoltage level to collapse toward ground over time. The Select signalsindicate to the external power supply 205 the voltage level at which thelogic supply, Vdd, should be maintained. Circuitry 202 can be referredto as a nonpersistent low voltage logic supply domain implementingcircuitry 206 (e.g., microprocessor logic circuits, memory circuits,clocks, latches, etc.). This nonpersistent low voltage supply domain isreferred to as such, since the circuits 206 can be turned off forvarious reasons as described previously. The constant I/O domain 203implements I/O drivers and receivers 207 for supplying data signals tothe off-chip domain. It is typical that such drivers and receivers 207require higher supply voltages, and thus in this example, a 3.3V supplyis utilized by domain 203, while the lower 1.8-1.0V supply is used bydomain 202.

[0023] When data signals are transferred from circuitry 206 to driversand receivers 207, there is a need for level shifters 100 to transferthe data from the lower voltage supply domain to the higher voltagesupply domain. And, as discussed above, there may be a need for theselevel shifters 100 to operate under conditions where power is terminatedfrom the low voltage logic supply domain 202.

[0024] Referring to FIG. 1, there is illustrated level shifter 100 infurther detail. Devices 101, 104, 105, 106, 110, 111, 113, and 114 areNFET CMOS (complementary metal-oxide semiconductor) devices, whiledevices 102, 103, 107, 108, 109, and 112 are PFET CMOS devices. However,the present invention may also be utilized with other types of switchingcircuits with equivalent functionality.

[0025] PFETs 102 and 103 and NFETs 101 and 104 form a NOR gate. WhenHOLD is high, the output node 120 of this gate is held low. When HOLD islow, the output node 120 of the gate is the logical inversion of theinput DATA IN. PFETs 107 and 108 and NFETs 105 and 106 form a NOR gate.When HOLD is high, the output node 121 of this gate is held low. WhenHOLD is low, the output node 121 of the gate has the same value as thesignal DATA IN. PFETs 109 and 112 and NFETs 111 and 113 form across-coupled inverter which is a storage cell. When HOLD is high, bothNOR gates have a low output value, NFETs 110 and 114 are off, and thecross-coupled inverter maintains the state of the output DATA OUT. WhenHOLD is low and the output node 120 of the NOR formed by NFETs 101 and104 and PFETs 102 and 103 is high, NFET 114 is turned on and the outputDATA OUT is pulled low. The inverter formed by NFET 111 and PFET 109reinforces this condition. When HOLD is low and the output node 121 ofthe NOR formed by NFETs 105 and 106 and PFETs 107 and 108 is high, NFET110 is turned on and the input node 122 to the inverter formed by PFET112 and NFET 113 is driven low, and the output DATA OUT is driven high.The inverter formed by NFET 111 and PFET 109 reinforces this condition.

[0026] In either instance, if the Vdd power supply is to be removed,first the HOLD signal is activated to a high state. This effectivelyisolates level shifter 100 from the Vdd power supply and isolates thelow power circuits from the higher power supply circuits, and in turnmaintaining the state of the data signal present in the level shifter.

[0027] Although the present invention and its advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.

What is claimed is:
 1. A level shifter comprising: a data input node; afirst inverter having its input connected to the data input node; asecond inverter connected to an output of the first inverter; a dataoutput node; a latch having its output connected to the data outputnode; a first NFET connected between an input of the latch and a groundpotential, the first NFET having its gate electrode connected to anoutput of the second inverter; and a second NFET connected between thedata output node and the ground potential, the second NFET having itsgate electrode connected to the output of the first inverter.
 2. Thelevel shifter as recited in claim 1, further comprising: a firstswitching device connected between the output of the first inverter andthe ground potential, wherein the first switching device receives a holdsignal at its gate electrode.
 3. The level shifter as recited in claim1, further comprising: a first switching device connected between theoutput of the second inverter and the ground potential, wherein thefirst switching device receives a hold signal at its gate electrode. 4.The level shifter as recited in claim 2, further comprising: a secondswitching device connected between the output of the second inverter andthe ground potential, wherein the second switching device receives thehold signal at its gate electrode.
 5. The level shifter as recited inclaim 1, further comprising: a first switching device connected betweenthe first inverter and a first power supply having a first potential,wherein the first switching device receives a hold signal at its gateelectrode.
 6. The level shifter as recited in claim 1, furthercomprising: a first switching device connected between the secondinverter and a first power supply having a first potential, wherein thefirst switching device receives a hold signal at its gate electrode. 7.The level shifter as recited in claim 6, further comprising: a secondswitching device connected between the first inverter and the firstpower supply having the first potential, wherein the second switchingdevice receives the hold signal at its gate electrode.
 8. The levelshifter as recited in claim 4, further comprising: a third switchingdevice connected between the first inverter and a first power supplyhaving a first potential, wherein the third switching device receivesthe hold signal at its gate electrode; and a fourth switching deviceconnected between the second inverter and the first power supply havingthe first potential, wherein the fourth switching device receives thehold signal at its gate electrode.
 9. The level shifter as recited inclaim 1, wherein the first and second inverters are energized by a firstpower supply having a first potential, and wherein the latch isenergized by a second power supply having a second potential.
 10. Thelevel shifter as recited in claim 9, wherein the first potential is 1.8volts, and the second potential is 3.3 volts.
 11. The level shifter asrecited in claim 1, further comprising circuitry for isolating the firstand second inverters from the latch.
 12. A level shifter comprising:first circuitry for receiving a data signal having a voltage swing fromground to 1.8 volts; second circuitry for converting the data signal tohave a voltage swing from ground to 3.3 volts; and an output node foroutputting the data signal with the voltage swing from ground to 3.3volts.
 13. The level shifter as recited in claim 12, further comprising:circuitry for isolating the first circuitry from the second circuitryafter the data signal has been converted to have the voltage swing fromground to 3.3 volts.
 14. The level shifter as recited in claim 13,further comprising: circuitry for disconnecting the first circuitry froma power supply providing the voltage swing from ground to 1.8 volts. 15.The level shifter as recited in claim 12, wherein the first circuitrycomprises first and second NOR gates and wherein the second circuitrycomprises a storage cell.
 16. A data processing system comprising: amicroprocessor and accompanying circuitry outputting data signals with avoltage swing magnitude of 1.8 volts; level shifter circuitry forconverting the voltage swing magnitude of the data signals from 1.8volts to 3.3 volts; and input/output circuitry for receiving the datasignals with the voltage swing magnitude of 3.3 volts.
 17. The system asrecited in claim 16, wherein the level shifter circuitry furthercomprises: first circuitry for receiving the data signals having avoltage swing from ground to 1.8 volts; and second circuitry forconverting the data signals to have a voltage swing from ground to 3.3volts.
 18. The system as recited in claim 17, further comprising:circuitry for isolating the first circuitry from the second circuitryafter the data signals have been converted to have the voltage swingfrom ground to 3.3 volts.
 19. The system as recited in claim 18, furthercomprising: circuitry for disconnecting the first circuitry from a powersupply providing the voltage swing from ground to 1.8 volts.
 20. Thesystem as recited in claim 16, wherein the level shifter circuitryfurther comprises: a data input node for receiving the data signals; afirst inverter having its input connected to the data input node; asecond inverter connected to an output of the first inverter; a dataoutput node; a latch having its output connected to the data outputnode; a first switch connected between an input of the latch and aground potential, and having its gate electrode connected to an outputof the second inverter; and a second switch connected between the dataoutput node and the ground potential, and having its gate electrodeconnected to the output of the first inverter.
 21. The system as recitedin claim 20, further comprising circuitry for isolating the first andsecond inverters from the latch.
 22. A level shifter comprising: a datainput node; a first NOR gate coupled to the data input node; a secondNOR gate coupled to an output of the first NOR gate; a storage cellcoupled to an output of the second NOR gate; and a data output nodecoupled to an output of the storage cell.
 23. The level shifter asrecited in claim 22, further comprising a first NFET coupled between thefirst NOR gate and the second NOR gate.
 24. The level shifter as recitedin claim 23, further comprising a second NFET coupled to the output ofthe first NOR gate and to the data output node.
 25. The level shifter asrecited in claim 22, wherein the first and second NOR gates are poweredby a first voltage supply, and wherein the storage cell is powered by asecond voltage supply, wherein the first and second voltage supplieshave different voltages.
 26. The level shifter as recited in claim 23,wherein the first and second NOR gates are configured to receive a holdsignal.
 27. The level shifter as recited in claim 22, wherein the firstNOR gate receives a hold signal and a nonpersistent low voltage datasignal, and generates a first NOR output signal, wherein the second NORgate receiver the hold signal and the first NOR output signal, andgenerates a second NOR output signal, the level shifter furthercomprising circuitry for coupling the first NOR output signal and thesecond NOR output signal to complimentary inputs of the storage cellgenerating a persistent high voltage data signal.